Power sensitivity of low-voltage CMOS current-mode circuits

Author

Yuan, Fei

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Polytech. Univ., Toronto, Ont., Canada

Volume

3

fYear

2004

Firstpage

1741

Abstract

This paper proposes an analytical method for analysis of the power sensitivity of low-voltage CMOS current-mode circuits. The power sensitivity is analyzed using the transfer function from the supply voltage to the biasing currents at both low and high frequencies. We show that conventional voltage-mode circuits are sensitive to switching noise and are therefore not particularly suitable for gigabit per second serial links where timing jitter is critical to BER of the links. Current-mode circuits, on the other hand, exhibit much less power sensitivity. We further show that cascode techniques are effective in reducing the power sensitivity of low-voltage CMOS current-mode circuits. Several current-controlled oscillators are implemented using TSMC 0.18 μm CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results are presented.

Keywords

CMOS integrated circuits; circuit simulation; current-mode circuits; error statistics; low-power electronics; oscillators; transfer functions; 0.18 micron; BER; BSIM3.3 device models; Spectre; TSMC; biasing currents; cascode techniques; current-controlled oscillators; current-mode circuits; low-voltage CMOS; power sensitivity; simulation; supply voltage; transfer function; Bit error rate; CMOS technology; Circuit noise; Current mode circuits; Frequency; Oscillators; Switching circuits; Timing jitter; Transfer functions; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1349751

Filename

1349751