Design of a high-speed block interleaving/deinterleaving architecture for wireless communication applications

Author

Yu, Chu ; Yen, Mao-Hsu ; Hsiung, Pao-Ann ; Chen, Sao-Jie

Author_Institution

Dept. of Electron. Eng., Nat. ILan Univ., Yilan

fYear

2009

Firstpage

1

Lastpage

2

Abstract

This paper presents a high-speed block interleaver/deinterleaver designed to prevent burst errors in wireless communications. Using FIFO banks, our proposed architecture is a high-speed design that owns lower hardware complexity and consumes lower power dissipation. Especially, the simple finite-state-machine control unit used in our design can provide an arbitrary column-wise permutation for the block interleaver.

Keywords

finite state machines; radiocommunication; FIFO banks; finite-state-machine control unit; first-in-fnst-out structure; high-speed block deinterleaving architecture; high-speed block interleaving architecture; lower hardware complexity; lower power dissipation consumption; wireless communication applications; Application software; Clocks; Communication standards; Communication system control; Computer architecture; Computer science; Design engineering; Hardware; Interleaved codes; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

978-1-4244-4701-5

Electronic_ISBN

978-1-4244-2559-4

Type

conf

DOI

10.1109/ICCE.2009.5012220

Filename

5012220