• DocumentCode
    1712501
  • Title

    Efficient custom instruction enumeration for extensible processors

  • Author

    Xiao, Chenglong ; Casseau, Emmanuel

  • Author_Institution
    Irisa, Univ. of Rennes I, France
  • fYear
    2011
  • Firstpage
    211
  • Lastpage
    214
  • Abstract
    In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically custom instructions from a high-level application code. In this paper, we propose an efficient and flexible algorithm for the exact enumeration of custom instructions. The algorithm can be tuned to generate all possible patterns or only connected patterns. Compared to a previously proposed well-known algorithm, our algorithm can achieve orders of magnitude speedup.
  • Keywords
    instruction sets; microprocessor chips; base instruction set; custom instruction enumeration; extensible processors; general purpose processor; high level application code; magnitude speedup; power consumption; Benchmark testing; Computer architecture; GSM; Program processors; Runtime; Security; Transform coding; ASIPs; DFG; Extensible processors; custom instruction; custom instruction generation algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on
  • Conference_Location
    Santa Monica, CA
  • ISSN
    2160-0511
  • Print_ISBN
    978-1-4577-1291-3
  • Electronic_ISBN
    2160-0511
  • Type

    conf

  • DOI
    10.1109/ASAP.2011.6043270
  • Filename
    6043270