The Future of Nanometer SOC Design

Moore´s law (double the number of transistors at each new processing node) and classical semiconductor scaling (faster transistors running at lower power at each new processing node) parted company after the 130nm processing node. As a result, on-chip clock rates have stopped rising as fast and transistor power levels have stopped falling as quickly as they did in the past. This change in the trend demands a change to a system-design style that emphasizes the use of multiple processor cores (Leibson, 2006)