• DocumentCode
    1714354
  • Title

    Testability properties of local circuit transformations with respect to the robust path-delay-fault model

  • Author

    Hengster, Harry ; Drechsler, Rolf ; Becker, Bernd

  • Author_Institution
    Dept. of Comput. Sci., J.W. Goethe Univ., Frankfurt, Germany
  • fYear
    1994
  • Firstpage
    123
  • Lastpage
    126
  • Abstract
    We present a new approach to show that local circuit transformations which improve the area of a circuit preserve or improve robust path-delay-fault testability. In contrast to previously published methods which had to consider the whole circuit we examine only the subcircuits to be transformed. Furthermore, we present some new transformations which preserve or improve robust path-delay-fault testability
  • Keywords
    design for testability; logic testing; fault testability; global testability; local circuit transformations; robust path-delay-fault model; subcircuits; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Manufacturing processes; Minimization; Performance evaluation; Production; Robustness; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1994., Proceedings of the Seventh International Conference on
  • Conference_Location
    Calcutta
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-4990-9
  • Type

    conf

  • DOI
    10.1109/ICVD.1994.282669
  • Filename
    282669