Structural Verification in Minimal Time

During the design process of a complex system on chip most time is spent on the verification task. Structural verification is one of the primary strategies for testing. The authors present a method, where the structural testing effort is minimised. This is based on an algorithm, which identifies a set of linearly independent paths of a control flow graph together with a shortest path search. An example is given, where the effort for structural testing can be reduced by more than 40%