An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads

This paper addresses performance issues encountered in parallel functional gate-level simulation executed on multi-core machine. It demonstrates that a straightforward application of the multi-core simulation on a multi-core machine does not improve simulation performance. This is due to unbalanced partitioning, lack of sufficient concurrency in the design partitions, overhead due to communication between partitions, and synchronization overhead imposed by the simulator. We propose, implement and automate a generic (partitioning-independent) prediction-based solution to eliminate or minimize communication and synchronization overhead in an event-driven functional gate-level simulation on a multi-core machine. We demonstrate speedup obtained with this method on a set of real Opensource designs.