A multi-GHz PLL Built-In jitter extraction circuit for deep submicron technologies

Author

Ekekon, O. Kubilay ; Maltabas, Samed ; Margala, Martin

Author_Institution

Electr. & Comput. Eng. Dept., Univ. of Massachusetts Lowell, Lowell, MA, USA

fYear

2011

Firstpage

657

Lastpage

660

Abstract

This paper proposes a new Built-In Self Test architecture to detect time interval errors (TIE) of Phase-Locked Loops. A transient current sensor utilizing Flipped Voltage Follower (FVF) is used with a comparison block in the proposed topology. It is designed and verified for IBM 65 nm technology using 1 V supply voltage and capable of detecting both steady-state and transient currents up to 150 μA and 2 GHz frequency with a good accuracy. The proposed topology relies on the output voltage difference of transient sensors. Thus, it can be scalable as the technology shrinks and still be an effective method to detect new emerging faults.

Keywords

built-in self test; error detection; fault diagnosis; jitter; mixed analogue-digital integrated circuits; operational amplifiers; phase locked loops; transients; IBM; PLL; built-in self test architecture; deep submicron technologies; fault detection; flipped voltage follower; jitter extraction circuit; phase locked loops; size 65 nm; steady state current; time interval error detection; transient current sensor; voltage 1 V; Built-in self-test; Capacitance; Clocks; Inverters; Jitter; Phase locked loops; Transient analysis; Built-in Self Test; Jitter; Phase-Locked Loop; Time Interval Error;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design (ECCTD), 2011 20th European Conference on

Conference_Location

Linkoping

Print_ISBN

978-1-4577-0617-2

Electronic_ISBN

978-1-4577-0616-5

Type

conf

DOI

10.1109/ECCTD.2011.6043629

Filename

6043629