Modeling and experimental results of short channel annular MOS transistors

The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present a 2-D analytical I-V model for short-channel annular devices based on the solution of the Poisson equation in cylindrical coordinates and a simplified threshold voltage roll-off geometrical model.