Verification of AMBA Bus Model Using SystemVerilog

A verification environment to verify an ARM-based SoC (system-on-chip) by using system Verilog is presented in this paper. The new verification constructs can be easily reused for the objected-oriented feature of SystemVerilog. The paper also introduced how to design the AMBA (advanced microprocessors bus architecture) verification IP (intellectual property) by SystemVerilog, which include AHB (advanced high performance bus) master and AHB monitor. The verification IP can be reused to verify any AMBA protocol based SoC. To reduce the time spending in the verification, a reference model designing method is also discussed in the paper.