Design and implementation of all-digital receivers for mobile communications

The ability to turn advanced digital receiver concepts into silicon VLSI is fast becoming the key factor in competing successfully to realize commercial mobile communication systems. Behavioral synthesis is central to the next-generation of high-level VLSI design automation tools that allow designing at the algorithm level and rapid exploration of the VLSI architecture space. We demonstrate how to leverage behavioral synthesis technology in the design of digital transceivers. We propose and demonstrate a new DSP system design methodology where digital communications engineers can interactively explore detection and estimation algorithms, architectures, and their IC implementation. We demonstrate how the designer can explore algorithms and architectures using three examples from portable and mobile communication modem applications: an MFSK receiver for paging applications, a receiver front-end channel filter for a wideband modem, and a Viterbi decoder used for trellis-coded modulation. Using the methodology, we demonstrate how system designers can exercise control over algorithm parameters as well as architectural parameters such as hardware area, speed, and latency. This allows algorithm designers to quickly explore different VLSI architectures that execute the same algorithm