Simulating networks of superscalar processors

Simulating a network of complex superscalar processors with high accuracy and acceptable response time is a challenging problem. Using the technique called compiled simulation is probably the best known option to achieve this goal. However the existing compiled simulation approach requires major modifications to simulate superscalar and superpipelined architectures. This paper describes the difficulties in simulating such architectures and presents our solution. The major difference between our use of the compiled simulation technique and those in extant simulators is that we simulate, at compile time, the interactions between the functional units within and between basic code blocks using delay tables. This provides a much more accurate image of the actual execution. The paper describes our implementation of the approach for a single as well as a network of RS/6000 processors