A novel low voltage and high speed CMOS charge pump circuit

Author

Qiang, Fan ; Xiansong, Fu ; Pingjuan, Niu ; Guanghua, Yang ; Tiecheng, Gao

Author_Institution

Sch. of Inf. & Commun. Eng., Tianjin Polytech. Univ., Tianjin, China

Volume

3

fYear

2010

Abstract

A novel low voltage, high speed CMOS charge pump circuit for PLL is designed in the paper. The new structure refrains from the common spurious jump phenomenon, and is designed in N well mixed-signal Chartered 0.35μm CMOS process, simulated using Hspice. The results show the new circuit can operate under a 1V power supply, does not suffer from any waveform jitter. The output voltage has a relatively wide range, from 120mV up to 980mV. The operating frequency is 500MHz, and power consumption is low to 150μW.

Keywords

CMOS integrated circuits; SPICE; charge pump circuits; high-speed integrated circuits; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; Hspice; N well mixed-signal Chartered CMOS process; PLL; frequency 500 MHz; high speed CMOS charge pump circuit; low voltage CMOS charge pump circuit; operating frequency; output voltage; power consumption; size 0.35 mum; CMOS integrated circuits; Charge pumps; Frequency synthesizers; Logic gates; Phase locked loops; Power supplies; Synchronization; Phase locked loops (PLL); charge pump; high speed; low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems (ICSPS), 2010 2nd International Conference on

Conference_Location

Dalian

Print_ISBN

978-1-4244-6892-8

Electronic_ISBN

978-1-4244-6893-5

Type

conf

DOI

10.1109/ICSPS.2010.5555828

Filename

5555828