DocumentCode
1723152
Title
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Author
Lu, Zhonghai ; Xia, Lei ; Jantsch, Axel
Author_Institution
Dept. of Electron., Comput. & Software Syst. R. Inst. of Technol., Stockholm
fYear
2008
Firstpage
1
Lastpage
6
Abstract
In network-on-chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle the mapping problem in 2D mesh NoCs. In particular, we combine a clustering technique with the simulated annealing to speed up the convergence to near-optimal solutions. The clustering exploits the connectivity and distance relation in the network architecture as well as the locality and bandwidth requirements in the core communication graph. The annealing is cluster-aware and may be dynamically constrained within clusters. Our experiments suggest that simulated annealing can be effectively used to solve the mapping problem with a scalable size, and the combined strategy improves over the simulated annealing in execution time by up to 30% without compromising the quality of solutions.
Keywords
circuit optimisation; graph theory; integrated circuit design; network-on-chip; pattern clustering; simulated annealing; 2D mesh networks on chip application design; cluster-based simulated annealing; core communication graph; core-to-node mapping; intractable optimization problem; network architecture; Application software; Bandwidth; Delay; Design optimization; Mesh networks; Network-on-a-chip; Ores; Simulated annealing; Software systems; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Conference_Location
Bratislava
Print_ISBN
978-1-4244-2276-0
Electronic_ISBN
978-1-4244-2277-7
Type
conf
DOI
10.1109/DDECS.2008.4538763
Filename
4538763
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