Logical path delay distribution and transistor sizing

The merits of high performance design are high speed, low power consumption, and small silicon area. Area optimization could be achieved at different levels of the design abstraction. In this paper area-delay optimization technique that depends on library-free synthesis and transistor sizing is presented. This technique can be used to optimize the path delay or to minimize the path area for a specific given required time. It is generated depending on the CMOS inverter delay model, modified logical effort (MLE) model [A. Kabbani, D. Al-Khalili, and A. J. Al-Khalili (2004)] and the CMOS gate transition time model [A. Kabbani (2004)]. The proposed technique achieves better performance as compared to Synopsys´s design compiler. For a given required time, the presented technique saves on area-delay product by about 50% on the average.