Hybrid Localized SOI/bulk technology for low power system-on-chip

Author

Huguenin, J.L. ; Monfray, S. ; Bidal, G. ; Denorme, S. ; Perreau, P. ; Barnola, S. ; Samson, M.P. ; Arvet, C. ; Benotmane, K. ; Loubet, N. ; Liu, Q. ; Campidelli, Y. ; Leverd, F. ; Abbate, F. ; Clement, L. ; Borowiak, C. ; Cros, A. ; Bajolet, A. ; Handler

Author_Institution

STMicroelectronics, Crolles, France

fYear

2010

Firstpage

59

Lastpage

60

Abstract

This paper highlights the successful co-integration of Localized Silicon-On-Insulator (LSOI) devices and of bulk-Si I/O devices on the same chip. LSOI devices present good logic performances and very low mismatch values down to 1.2mV/μm. In addition, we show the backbiasing impact on LSOI SRAM bit-cells for stability improvement. This work also presents the co-integration of LSOI with bulk devices as a solution for the devices that are not compatible with thin-body technology. In particular, we demonstrate for the first time competitive bulk co-integrated ElectroStatic Discharge (ESD) protections.

Keywords

SRAM chips; circuit stability; electrostatic discharge; low-power electronics; silicon-on-insulator; system-on-chip; ESD protection; LSOI SRAM bit-cell; LSOI device; backbiasing impact; bulk-Si I/O device; electrostatic discharge; hybrid localized SOI/bulk technology; localized silicon-on-insulator; logic performance; low power system-on-chip; stability improvement; thin-body technology; Electrostatic discharge; Epitaxial growth; Logic gates; Performance evaluation; Random access memory; Silicon; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556119

Filename

5556119