20nm gate length trigate pFETs on strained SGOI for high performance CMOS

Author

Hutin, L. ; Cassé, M. ; Le Royer, C. ; Damlencourt, J.F. ; Pouydebasque, A. ; Xu, C. ; Tabone, C. ; Hartmann, J.-M. ; Carron, V. ; Grampeix, H. ; Mazzocchi, V. ; Truche, R. ; Weber, O. ; Batude, P. ; Garros, X. ; Clavelier, L. ; Vinet, M. ; Faynot, O.

Author_Institution

CEA LETI, Minatec, Grenoble, France

fYear

2010

Firstpage

37

Lastpage

38

Abstract

We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L_G=20nm; W=30nm; T_SiGe=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I_Dlin enhancement vs. SOI, I_ON=520μA/μm/I_OFF=130nA/μm at L_G=20nm and V_DS=-1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L_G=30nm). Combined to the intrinsic |V_th,p| lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.

Keywords

CMOS integrated circuits; Ge-Si alloys; MOSFET; hole mobility; semiconductor materials; silicon-on-insulator; SOI pFET; SiGe; SiGe on insulator; active area width; biaxial stress; electrostatic integrity; gate length trigate pFET; high performance CMOS; hole mobility; lateral elastic strain relaxation; pFET performance; pMOSFET; size 20 nm; strained SGOI; uniaxial stress; CMOS integrated circuits; Films; Logic gates; Silicon; Silicon germanium; Strain; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556130

Filename

5556130