Enhanced performance in SOI FinFETs with low series resistance by aluminum implant as a solution beyond 22nm node

Author

Ok, I. ; Young, C.D. ; Loh, W.-Y. ; Ngai, T. ; Lian, S. ; Oh, J. ; Rodgers, M.P. ; Bennett, S. ; Stamper, H.O. ; Franca, D.L. ; Lin, S. ; Akarvardar, K. ; Smith, C. ; Hobbs, C. ; Kirsch, P. ; Jammy, R.

Author_Institution

SEMATECH, Albany, NY, USA

fYear

2010

Firstpage

17

Lastpage

18

Abstract

We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <;20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate stacks. These attributes constitute a simple non-planar cMOS integration sequence for enhancing future high performance technology nodes.

Keywords

MOSFET; Schottky barriers; aluminium; silicon-on-insulator; SOI FinFET; aluminum implant; low series resistance; nonplanar cMOS integration sequence; short channel effects; FinFETs; Implants; Logic gates; Resistance; Silicides; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556138

Filename

5556138