Scheduling of DSP algorithms onto heterogeneous multiprocessors with inter-processor communication

In recent years a great deal of research has been conducted in the area of scheduling DSP data flow graphs (DFG) onto heterogeneous multiprocessing systems. However, there is not yet much research conducted for designing the scheduling algorithms that consider the inter-processor communication delays. This paper presents a novel technique to obtain time and processor schedules for cyclic DFGs representing DSP algorithms onto a heterogeneous multiprocessor systems by taking into consideration the inter-processor communication delays. In the proposed technique the communication delay between a pair of nodes of the different type is treated as a non-computing node, whereas that between a pair of nodes of the same type is taken into account by re-adjusting the firing times of the appropriate nodes of DFG. A simulation is carried to illustrate the proposed technique by applying it to a second-order digital filter. The results show the proposed technique can produce optimal time and processor-allocation schedules.