• DocumentCode
    1726226
  • Title

    Thermal reliability of fine pitch Cu-Cu bonding with self assembled monolayer (SAM) passivation for Wafer-on-Wafer 3D-Stacking

  • Author

    Peng, L. ; Li, H.Y. ; Lim, D.F. ; Gao, S. ; Tan, C.S.

  • Author_Institution
    Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
  • fYear
    2011
  • Firstpage
    22
  • Lastpage
    26
  • Abstract
    Three-dimensional integrated circuit (3D IC) is a technology that has the potential to overcome conventional scaling limits by reducing signal propagation delay and power consumption. Wafer-on-Wafer 3D-Stacking is a more practical option for high throughput manufacturing of 3D IC. It is important to ensure excellent electrical, mechanical and thermal properties of the bonding interface for robustness and long term reliability. Cu-Cu bonding has advantage in terms of excellent scalability which enables fine pitch vertical interconnect formation, providing a promising technique to meet future high density 3D IC requirement. In this work, we study the improvement in the contact resistance of the bonded Cu-Cu contacts with self-assembled monolayer (SAM) passivation prior to bonding and the thermal endurance of these contacts. A reduction of ~7.1% in the contact resistance is observed with the application of SAM for bonding at 350°C. We further show that SAM passivation is extendible to the formation of high density fine-pitch Cu-Cu bonding with 100% bonding yield that sustains extreme thermal cycling.
  • Keywords
    bonding processes; contact resistance; copper; integrated circuit interconnections; integrated circuit reliability; monolayers; passivation; self-assembly; three-dimensional integrated circuits; 3D IC; Cu; SAM; bonding interface; contact resistance; fine pitch bonding; fine pitch vertical interconnect formation; passivation; scalability; self assembled monolayer; signal propagation delay; temperature 350 degC; thermal cycling; thermal endurance; thermal reliability; three-dimensional integrated circuit; wafer-on-wafer 3D-stacking; Bonding; Contact resistance; Copper; Passivation; Surface cleaning; Three dimensional displays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-61284-497-8
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2011.5898485
  • Filename
    5898485