Advanced error prediction LDPC for high-speed reliable TLC nand-based SSDs

Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash´s capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower V_TH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved reliability for Multi-Level-Cell (MLC) NAND flash [4]. However, in EP-LDPC program disturb is not modeled, so precision is limited, especially in short data retention <; 2 days. Here, AEP-LDPC is proposed for TLC NAND flash. By considering effects of program disturb, data retention and floating-gate capacitive coupling, the most accurate SSDs can be realized, with high speed read capability. The SSD´s data-retention time increases by more than 12^x, decode iterations decrease 57% and acceptable TLC NAND BER increases by more than 2.8 ×.