A reliability-boosted ferroelectric random access memory with random-dynamic reference cells

Generating reference signal is indispensable and challenging in ferroelectric random access memory using one-transistor and one-capacitor architecture. This work presents an architecture with random-dynamic reference scheme for high speed and high reliability application. The detailed scheme and operating principle are illustrated. By rewriting memory cells and reference cells simultaneously after read process, the cycle time can be reduced. The data rewritten into reference cells are related to the data in memory cells, which can realize rewriting randomly “0” or “1” into reference cells. This method can balance the switch times of the pair of reference capacitors and restrain the floating of reference voltage generated for data read process, resulting in boosted reliability in the proposed architecture. A prototype based on the proposed architecture is fabricated and verified. It is exhibited that the proposed method can effectively reduce the cycle time and improve the operating speed.