Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits

We experimentally demonstrate, for the first time, a new metallic carbon nanotube (CNT) removal technique that can be readily scaled to full-wafer-scale. Existing metallic CNT removal techniques either do not remove enough metallic CNTs, or are not VLSI-compatible, or impose very large area costs when applied to wafer-scale VLSI (up to 200%). In contrast, our new technique retains VLSI-compatibility, achieves high I_on/I_off of up to 10⁶ and, at the same time, is readily scalable to full-wafer-level with <;1% area cost. Using our new technique, we demonstrate cascaded CNFET logic circuits immune to CNT imperfections such as mis-positioned and metallic CNTs.