Path Delay Fault Design For Test and Testability Analysis of Conditional Sum Adders

Conditional sum adders (CSA) are kinds of high-speed adders and the existing delay faults have crucial influence on their performance. Detail path delay fault testability analysis is proposed and a design-for-test scheme with low overhead and low size of test set is presented which can guarantee single path propagating hazard-free fully robust path delay fault testability of CSA. This is the strictest requirement for path delay fault testing. Based on the scheme, a test set of minimal size is derived by exploiting its structural property and parallel testing.