DocumentCode
1731060
Title
A common architecture for the DWT and IDWT
Author
Vishwanath, Mohan ; Owens, Robert M.
Author_Institution
Comput. Sci. Lab., Xerox Palo Alto Res. Center, CA, USA
fYear
1996
Firstpage
193
Lastpage
198
Abstract
This paper presents an architecture which is equally efficient at computing both the discrete wavelet transform (the DWT) and the inverse discrete wavelet transform (the IDWT). Given the seemingly fundamental difference between the structure of a DWT filter bank and the structure of an IDWT filter bank, it is somewhat surprising that such an architecture can be derived. Our architecture allows the building of a single chip which can efficiently compute both transforms. Tandem use of the architecture (→DWT→IDWT→) is simplified by the fact that the j´th octave is generated by the architecture when it is in DWT mode at the sane rate at which it is consumed by the architecture when it is in IDWT mode
Keywords
digital signal processing chips; wavelet transforms; discrete wavelet transform; filter bank; inverse discrete wavelet transform; j´th octave; single chip; Buildings; Computer architecture; Computer science; Discrete wavelet transforms; Filter bank; Hardware; Investments; Processor scheduling; Scheduling algorithm; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
Conference_Location
Chicago, IL
ISSN
2160-0511
Print_ISBN
0-8186-7542-X
Type
conf
DOI
10.1109/ASAP.1996.542814
Filename
542814
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