DocumentCode
1731369
Title
Design and reliability analysis of pyramidal shape 3-layer stacked TSV die package
Author
Che, F.X. ; Chai, T.C. ; Lim, Sharon P S ; Rajoo, Ranjan ; Zhang, Xiaowu
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2011
Firstpage
1428
Lastpage
1435
Abstract
In this work, the reliability of a pyramidal shape 3-layer stacked TSV die package has been studied by experiments and finite element analysis (FEA). The originally designed microbumps are located peripherally around the edge of the die, which induces a concentrated bending force on the lower die when stacking the upper die. FEA simulation results show that such bump design induces large stress and deflection in the lower die during die stacking process. In this work, 3-point bend tests are conducted to determine the die strength. Actual die stacking experiments have been carried out and the results show that the bottom die cracks when stacking the middle die, and the bottom die cracks when stacking the top die even using a lower stacking force. Consistent results are achieved among FEA simulation, die strength bend test, and actual die stack experimental results. A new bump layout design has been optimized with some dummy bumps added on the central area of the die to directly support bending force induced by die stacking. The new design significantly reduces die stress and deflection. Eventually, a successful die stacking process is achieved even using a larger stacking force. The optimal bump layout design also leads to a lower package warpage in solder reflow process compared to the original bump layout design.
Keywords
bending; finite element analysis; integrated circuit layout; integrated circuit packaging; integrated circuit reliability; solders; three-dimensional integrated circuits; 3-point bend testing; bump layout design; die stacking process; die strength bend test; finite element analysis; microbump; pyramidal shape 3-layer stacked TSV die package; reliability analysis; solder reflow process; Force; Layout; Load modeling; Semiconductor device modeling; Simulation; Stacking; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location
Lake Buena Vista, FL
ISSN
0569-5503
Print_ISBN
978-1-61284-497-8
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2011.5898699
Filename
5898699
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