Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

Author

Frank, M.M. ; Paruchuri, V.K. ; Narayanan, V. ; Bojarczuk, N. ; Linder, B. ; Zafar, S. ; Cartier, E.A. ; Gusev, E.P. ; Jamison, P.C. ; Lee, K.L. ; Steen, M.L. ; Copel, M. ; Cohen, S.A. ; Maitra, K. ; Wang, X. ; Kozlowski, P.M. ; Newbury, J.S. ; Medeiros,

Author_Institution

IBM Semicond. R&D Center, Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2005

Firstpage

97

Lastpage

98

Abstract

We demonstrate poly-Si/high-k gate stacks suitable for successful implementation in low power technologies. An optimized gate dielectric process was employed to suppress the large pFET threshold voltage shift commonly found with Hf-based gate dielectrics, reducing it to -0.2 V, while preserving pFET and nFET device performance.

Keywords

dielectric materials; field effect transistors; hafnium; low-power electronics; gate dielectric process; gate dielectrics; high-k gate stack; low power technology; nFET; pFET; poly-Si gate stack; threshold voltage shift; Degradation; Dielectric devices; Doping; Electron mobility; Hafnium; High K dielectric materials; High-K gate dielectrics; Rapid thermal annealing; Scalability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

ISSN

1930-8868

Print_ISBN

0-7803-9058-X

Type

conf

DOI

10.1109/VTSA.2005.1497093

Filename

1497093