Future of the MOS transistor in the nano-electronics era

Operational MOS transistors shorter than 10nm have been demonstrated at recent CMOS conferences. Yes, but their electrical characteristics remain by far behind the specifications (ITRS Roadmap). Does it mean that scaling is dead? Does it mean that the future of the Moore´s laws is menaced? We analyze these questions in detail and identify the physical causes behind the prospective CMOS performance deficiency. To illustrate the point, we show an anomalous scaling effect leading to a decrease in the transistor current when its channel is being shortened (a completely inverse effect with respect to the classical scaling). In the second part of the paper, we show how non-classical device structures: ultra thin single- and double-gate devices such as SOI, FinFET, SON (silicon on nothing) and new materials (HK-dielectrics, metallic gates, strained-Si) can help with retrieving healthy scaling. We also deliberate on how they can help to overcome or at least attenuate the problems with short-channel effect, with drain-induced barrier lowering effects, with high-field effects, with mobility degradation, with subthreshold leakage and finally with quantum effects, with discreteness of the matter etc., etc. In order to become reality, this huge potential of non-classical CMOS requires process availability and optimization based on a good understanding of the physics of these devices. We analyze the latter in terms of optimal silicon film thickness, optimal BOX thickness, ground-plane operation, optimal channel doping, threshold voltage adjustment with metallic gates and HK dielectrics, etc. etc. Finally, we show how these new device structures and materials prolongs the Moore´s laws up to the end of the roadmap (example of HP non-classical CMOS is also shown), and even beyond, thereby projecting CMOS into the nano-world.