A robustness-oriented design tool for the topology selection in analog synthesis

In order to solve two major bottlenecks of the analog design flow: the time-to-market and the production yield, we introduce in this paper a design tool for measuring the robustness capability of the analog circuit topologies with the guarantee of fulfilling all the design specifications. With this measure, we can describe the feasible subspace by using the set inversion algorithm. A robustness estimation example of a differential pair of a miller CMOS OTA is shown to illustrate this method.