DocumentCode
1733727
Title
A Cost Analysis Framework for Multi-core Systems with Spares
Author
Shamshiri, Saeed ; Lisherness, Peter ; Pan, Sung-Jui ; Cheng, Kwang-Ting
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA
fYear
2008
Firstpage
1
Lastpage
8
Abstract
It becomes increasingly difficult to achieve a high manufacturing yield for multi-core chips due to larger chip sizes, higher device densities, and greater failure rates. By adding a limited number of spare cores to replace defective cores either before shipment or in the field, the effective yield of the chip and its overall cost can be significantly improved. In this paper, we propose a yield and cost analysis framework to better understand the dependency of a multi-core chip´s cost on key parameters such as the number of cores and spares, core yield, and defect coverage of manufacturing and in-field testing. Our analysis shows that we can eliminate the burn-in process when we have some spare cores for in-field recovery. We demonstrate that a high defect coverage for in-field testing, a necessity for supporting in-field recovery, is essential for overall cost reduction. We also illustrate that, with in-field recovery capability, the reliance on high quality manufacturing testing is significantly reduced.
Keywords
cost reduction; electronic equipment manufacture; electronic equipment testing; microprocessor chips; cost analysis; cost reduction; in-field testing; manufacturing testing; manufacturing yield; multicore chips; multicore systems; Automatic testing; Costs; Field programmable gate arrays; Logic devices; Manufacturing processes; Multicore processing; Programmable logic arrays; Pulp manufacturing; System testing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-2402-3
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2008.4700562
Filename
4700562
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