Multi-path fan-shaped compliant off-chip interconnects

With the introduction of on-chip low-K dielectric materials, it is increasingly important to reduce on-chip stresses so that the low-K dielectric material will not crack or delaminate. One way to reduce the thermo-mechanical stresses is to introduce compliant structures between the die and the substrate and thus to decouple the die from the substrate. Thus, mechanically compliant interconnects have been pursued by several researchers to decouple the die from the substrate and to increase the reliability of the chip-substrate assembly. In this work, we report the design, the fabrication, and the modeling of innovative multi-path fan-shaped off-chip compliant interconnects. The proposed interconnects can be fabricated at the wafer-level and are cost-effective, can be of fine pitch and scalable, and will have redundant electrical paths. Fan-shaped interconnects with two, three, or four arcs have been designed. In these interconnects, the outer ends of the arcs will be connected to the die pad through columns, while the center or hub of the arcs will be connected to the substrate pad through solder. Through mechanical simulations, it is seen that the interconnects will have a compliance that is several orders of magnitude greater than the compliance of typical solder bump interconnects. Scaled prototypes of the interconnects have been fabricated, and load versus displacement for these interconnects have been experimentally measured. Simulations were also carried out through the entire range of deformation as in experiments, and it is seen that the simulation results have similar trends as the experimental data. Based on this study, it appears that multi-path fan-shaped interconnects could potentially offer a new suite of compliant interconnects for further study and research.