DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG

The implementation and validation of a common DFT architecture for a new product family of PowerPC based microprocessors for various automotive applications supporting highest quality levels and low-cost test is a big challenge. When this new architecture has to satisfy the requirements of two semiconductor companies using two different CAD flows based on different ATPG tools coming with incompatible on-chip scan compression solutions, the task becomes even more complex. This paper describes the result of this major effort and shows the problems encountered along the way.