• DocumentCode
    1735567
  • Title

    Low-voltage green transistor using ultra shallow junction and hetero-tunneling

  • Author

    Bowonder, Anupama ; Patel, Pratik ; Jeon, Kanghoon ; Oh, Jungwoo ; Majhi, Prashant ; Tseng, Hsing-Huang ; Hu, Chenming

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA
  • fYear
    2008
  • Firstpage
    93
  • Lastpage
    96
  • Abstract
    A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.
  • Keywords
    low-power electronics; tunnel transistors; dielectric interface; hetero-tunnel transistor; hetero-tunneling; heterostructure; low power electronics; low voltage electronics; low voltage green transistor; quantum mechanical tunneling theory; ultra shallow junction; Electrons; Energy consumption; High-K gate dielectrics; MOSFETs; Medical simulation; Quantum mechanics; Thermal management; Transistors; Tunneling; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Junction Technology, 2008. IWJT '08. Extended Abstracts - 2008 8th International workshop on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-1737-7
  • Electronic_ISBN
    978-1-4244-1738-4
  • Type

    conf

  • DOI
    10.1109/IWJT.2008.4540025
  • Filename
    4540025
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1735567