Power-Aware DFT - Do we really need it?

Scan-based vectors dissipate much more power compared to the functional operation of a device. These vectors are known to cause IR drop, voltage droop, hot spots, etc. Consequently, there is an increase in demand for power reporting, insertion of DFT logic to control power dissipation during shift as well as capture, design partitioning, imposing power threshold limits during ATPG, etc. But there are some basic questions that need to be answered. Is there a real power dissipation problem during test mode? Is it impacting yield today? How do we make sure that power dissipation during test correlates well with the functional mode? Are we under-testing our design if we restrict power? This panel provides a forum to ask these tough questions to the experts and help us understand how to address the challenges in the near future.