A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-μm CMOS

Author

Tálebzadeh, Jafar ; Hasanzadeh, M.R. ; Yavari, Mohammad ; Shoaei, Omid

Author_Institution

Dept. of Electr. & Comput. Eng., Tehran Univ., Iran

Volume

3

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

This paper describes a 10-bit 150 MS/s CMOS parallel pipeline ADC. The converter includes four parallel interleaved pipeline A/D converters with analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators that match the offsets and gains of time-interleaved ADC channels. With monolithic analog background calibration, the SNDR in all corner cases (SS, SF, FS, FF, and TT) and temperature between -40°C to 85°C is better than 57 dB. The power consumption is 1200 mW at a 3.0 V supply voltage. This work is achieved in a 0.6 μm CMOS process.

Keywords

CMOS integrated circuits; adaptive signal processing; analogue-digital conversion; calibration; integrating circuits; low-power electronics; mixed analogue-digital integrated circuits; pipeline processing; -40 to 85 degC; 0.6 micron; 10 bit; 1200 mW; 3.0 V; CMOS; SNDR; adaptive signal processing; analog background calibration; gains; mixed signal integrators; offsets; parallel interleaved pipeline A/D converters; power consumption; Adaptive signal processing; Analog-digital conversion; Calibration; Energy consumption; Multiplexing; Pipelines; Signal processing; Temperature; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010178

Filename

1010178