DocumentCode
1737236
Title
Diagnosis of Logic-to-chain Bridging Faults
Author
Liu, Wei-Chih ; Tsai, Wei-Lin ; Lin, Hsiu-Ting ; Li, James Chien-Mo
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ.
fYear
2008
Firstpage
1
Lastpage
1
Abstract
We propose five logic-to-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-to-chain bridging faults, unlike any existing fault, depend on the previous scan inputs as well as primary inputs. An accurate diagnosis technique is presented to locate logic-to-chain bridging faults. In addition, a bridging pair extraction algorithm is proposed to quickly extract bridging net pairs from the layout. Experimental results on ISCAS benchmark circuits show that, on the average, logic-to-chain bridging faults can be diagnosed within an accuracy of three bridging pairs. The technique is still applicable when only ten failing patterns are recorded on the tester.
Keywords
combinational circuits; fault diagnosis; integrated circuit modelling; logic testing; ISCAS benchmark circuits; bridging pair extraction algorithm; combinational logic; logic-to-chain bridging fault diagnosis; primary inputs; ten failing patterns; Benchmark testing; Circuit faults; Circuit testing; Fault diagnosis; Logic testing; Routing; Time measurement; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2008. ITC 2008. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-2402-3
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2008.4700695
Filename
4700695
Link To Document