Transistors optimization of CMOS logic structures for high performance IC

In a high-performance IC design, the need for carefully optimized basic gates has become essential. The guidelines for the optimization procedure in high-performance digital circuits include both the limitations of integrated area and the increasing speed, but power consumption must also be considered with increasing care in current applications. This paper describes the structure of an optimization tool developed using some different algorithms, in particular those that permit multi-objective optimization. The aim is to have an optimization tool which is flexible to variable constraints, to the introduction of new parameters and to developing algorithms with different qualities and performances.