A cell library of scalable neural network classifiers for rapid low-power vision and cognition systems design

The application of neural classifiers in intelligent systems, both as general purpose chips or as dedicated cells in larger VLSI designs, has been an active field of research due to the inherent properties of fault tolerance, graceful degradation, and adaptation capability. Underlying systems for, e.g., biometrics, multimedia, advanced image coding, or automotive tasks, enjoy increasing industrial acceptance and application. Tight application constraints such as, e.g., size, speed, performance, and especially power consumption give increasing incentive to dedicated integrated system implementations, exploiting bio-inspiration and opportunistic design techniques in analog or mixed-signal circuits and systems. In this work, we investigate the major classification techniques with regard to their performance, training properties, and implementation aptitude with special focus on power dissipation and area consumption. A cell library implementing the basic VLSI building blocks for scalable classifier design is progressed in our work. Application examples of this library for system-level VLSI implementation, e.g., for a low-power eye-tracker, are presented. Our work contributes to a research effort with the objective to develop and advance a dedicated top-down design methodology and design flow for integrated vision and cognition systems employing opportunistic and parsimonious design style