• DocumentCode
    173831
  • Title

    Stuck-at fault diagnosis in scan chains

  • Author

    Dounavi, Helen-Maria ; Tsiatouhas, Y.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of Ioannina, Ioannina, Greece
  • fYear
    2014
  • fDate
    6-8 May 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Scan chain diagnosis turns out to be an important yield enhancement factor in modern nanometer technologies. An easy to implement and cost effective design-for-diagnosis technique is presented. The proposed technique is compatible with the standard scan chain architecture and provides fast stuck-at fault diagnosis capabilities, at the maximum resolution, through simple operations, using only four predefined diagnosis vectors and independently of any test response compaction circuitry at the outputs of the scan chains.
  • Keywords
    boundary scan testing; design for testability; fault location; integrated circuit yield; design-for-diagnosis technique; diagnosis vectors; scan chain diagnosis; stuck-at fault diagnosis; yield enhancement factor; Circuit faults; Clocks; Computer architecture; Flip-flops; Logic gates; MOSFET; Scan chain diagnosis; fault location; yield enhancement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2014 9th IEEE International Conference On
  • Conference_Location
    Santorini
  • Type

    conf

  • DOI
    10.1109/DTIS.2014.6850663
  • Filename
    6850663