DocumentCode
1738755
Title
Processor-farm model for parallel computation of fixed-polarity Reed-Muller expansions
Author
Tan, E.C. ; Loh, P.K.K.
Author_Institution
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore
Volume
2
fYear
2000
fDate
2000
Firstpage
1
Abstract
A Reed-Muller logic function is usually derived from a given Boolean expression by applying an appropriate conversion technique. Existing conversion algorithms are sequential in nature and are inefficient when the number of variables is large. We propose a processor-farm paradigm which allows the conversion to be performed by a few processors in a parallel and efficient manner
Keywords
Reed-Muller codes; formal logic; logic design; parallel algorithms; parallel architectures; Boolean expression; Reed-Muller logic function; conversion algorithms; efficiency; fixed-polarity Reed-Muller expansions; parallel computation; processor farm model; variable numbers; Boolean functions; Circuit testing; Computational modeling; Concurrent computing; Counting circuits; Distributed computing; Logic functions; Parallel processing; Programmable logic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2000. Proceedings
Conference_Location
Kuala Lumpur
Print_ISBN
0-7803-6355-8
Type
conf
DOI
10.1109/TENCON.2000.888377
Filename
888377
Link To Document