DocumentCode
1739864
Title
Parallel algorithms for detecting hazards in combinational logic circuits
Author
Tan, E.C.
Author_Institution
Sch. of Comput. Eng., Nanyang Technol. Inst., Singapore
Volume
1
fYear
2000
fDate
2000
Firstpage
177
Abstract
Data and control parallelism algorithms are described for a matrix method which detects and locates the presence of logic hazards in combinational logic circuits. Examples are given for illustration
Keywords
combinational circuits; hazards and race conditions; matrix algebra; parallel algorithms; combinational logic circuits; control parallelism algorithms; data parallel algorithms; hazards detection; logic hazards; matrix method; Circuit analysis; Circuit testing; Combinational circuits; Hazards; Input variables; Logic; Parallel algorithms; Parallel processing; Propagation delay; Pulse circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2000. Proceedings
Conference_Location
Kuala Lumpur
Print_ISBN
0-7803-6355-8
Type
conf
DOI
10.1109/TENCON.2000.893565
Filename
893565
Link To Document