A 29 dBm 1.9 GHz class B power amplifier in a digital CMOS process

Author

Asbeck, Per ; Fallesen, Carsten

Author_Institution

Nokia Denmark A/S, Denmark

Volume

1

fYear

2000

fDate

2000

Firstpage

474

Abstract

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital CMOS process with low resistivity substrate. The output power is 29 dBm in a 50 ohm load. A design method, based on sweeping the loss and the resonance frequency of an LC tank to determine large signal parameters of the output transistor, is presented. Based on this method proper values for on-chip interstage matching and off-chip output matching can be derived. Measurement of a fabricated chip is compared with the simulated circuit

Keywords

CMOS analogue integrated circuits; MMIC power amplifiers; UHF integrated circuits; UHF power amplifiers; field effect MMIC; impedance matching; integrated circuit measurement; network parameters; 1.9 GHz; 50 ohm; LC tank; class B power amplifier; digital CMOS process; large signal parameters; low resistivity substrate; off-chip output matching; on-chip interstage matching; output power; output transistor; resonance frequency; CMOS process; Circuit simulation; Conductivity; Design methodology; Impedance matching; Power amplifiers; Power generation; Resonance; Resonant frequency; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911582

Filename

911582