Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures

Author

Adaos, K. ; Alexiou, G. ; Kanopoulos, N.

Volume

1

fYear

2000

fDate

2000

Firstpage

567

Abstract

This paper presents the development of a family of bit-serial FIR filters with dynamically reprogrammable coefficients. The filters are described in standard VHDL, automatically produced by a parameterized software tool. Reusability was verified by synthesizing the HDL code for different ASIC and FPGA platforms. Efficiency was measured by implementation and accurate timing simulation in ALTERA FPGAs. The proposed filters are designed for use in serial data-flow computation

Keywords

FIR filters; circuit CAD; circuit simulation; digital arithmetic; hardware description languages; multiplying circuits; programmable filters; timing; ALTERA FPGAs; ASIC platforms; FPGA platforms; HDL code; bit-serial FIR filters; dynamically reprogrammable coefficients; parameterized software tool; reprogrammable coefficients; reusability; reusable serial FIR filters; serial dataflow architectures; standard VHDL; timing simulation; Application specific integrated circuits; Computer architecture; Data engineering; Design engineering; Emulation; Field programmable gate arrays; Finite impulse response filter; Guidelines; Hardware design languages; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.911603

Filename

911603