• DocumentCode
    1744317
  • Title

    Methodology of functional test synthesis and verification for VLSI systems

  • Author

    Hudec, Ján

  • Author_Institution
    Fac. of Electr. Eng., Slovak Tech. Univ., Bratislava, Slovakia
  • fYear
    2000
  • fDate
    16-16 June 2000
  • Firstpage
    61
  • Lastpage
    66
  • Abstract
    This paper deals with a methodology for test synthesis and verification of VLSI and ASIC systems using an automatic functional test generator (AFTG). The proposed approach-the functional test generation methodology is based on specification and functional description of VLSI/ASIC systems. The determination of the test efficiency of instructions mixes is discussed.
  • Keywords
    VLSI; application specific integrated circuits; automatic test pattern generation; formal verification; ASIC systems; VLSI systems; automatic functional test generator; functional test synthesis; functional verification; test synthesis; Application specific integrated circuits; Automatic testing; Circuit testing; Design automation; Information technology; Network synthesis; Production; Software testing; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Technology Interfaces, 2000. ITI 2000. Proceedings of the 22nd International Conference on
  • Conference_Location
    Pula, Croatia
  • ISSN
    1330-1012
  • Print_ISBN
    953-96769-1-6
  • Type

    conf

  • Filename
    915820
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1744317