Evaluation of substrate noise in CMOS and low-noise logic cells

The substrate noise generated by conventional CMOS and by different low-noise logic families is investigated by computer simulation of the circuits extracted from the layouts including the resistive substrate model. A widely used 0.8 μm CMOS technology is considered. It is found that, in small cells, the noise reduction with respect to CMOS is only significant in cells with complementary outputs. In large driver cells, considerable noise reduction can be obtained (without complementary outputs). One of the low-noise families, however, exhibits large noise for high supply wire inductance (in the examples here, with 2 V supply voltage, the noise is even higher than for CMOS cells, for inductance above 10 nH)