Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ~200 V to become ⩾3 kV