• DocumentCode
    1746680
  • Title

    Quality enhancement of reconfigurable multichip module systems by redundant utilization

  • Author

    Choi, M. ; Park, N. ; Lombardi, F. ; Piuri, V.

  • Author_Institution
    Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
  • Volume
    1
  • fYear
    2001
  • fDate
    21-23 May 2001
  • Firstpage
    204
  • Abstract
    This paper evaluates the quality-effectiveness of the utilization of redundancy in reconfigurable MCM (RMCM) systems. Due to the reconfigurability, a RMCM system can implement a device with different redundancy. Redundancy is determined by the requirement of the fault-tolerance (FT) of the device under implementation which is achieved by the feature of reconfigurability. No previous work has shown the effect of utilization of redundancy on quality-level (QL). In this paper, the tolerance to escaping from testing is introduced and referred to as the escape tolerance (ET). This can be achieved by utilizing a certain amount of redundancy and is studied by evaluating its effect on QL of RMCM under different amount of redundancy. Also, it is shown that the coverage of testing (FC) is improved by reconfiguration through numerical analysis. Hence, we derive the QL by relating the QL to the yield enhancement by reconfiguration; the effect of interconnection yield; the effect of ET to the QL; and the improvement in FC by reconfiguration. In the proposed approaches, appropriate combinatorial models are formulated to take into account parameters related to the redundancy and reconfiguration processes in RMCM systems. From extensive parametric results, a is shown that there exists a bound in the effectiveness of redundant utilization (i.e. the amount of redundancy) depending on the value of the RMCM yield and FC. Using the proposed approaches, redundant utilization of RMCM systems can be appropriately used to enhance the QL
  • Keywords
    design for testability; fault tolerance; field programmable gate arrays; integrated circuit yield; logic CAD; logic testing; multichip modules; reconfigurable architectures; redundancy; combinatorial models; coverage of testing; design for quality; escape tolerance; escaping from testing; fault-tolerance; field programmable systems; interconnection yield; quality enhancement; reconfigurability feature; reconfigurable multichip module systems; redundant utilization; yield enhancement; Computer science; Costs; Fault tolerance; Field programmable gate arrays; Integrated circuit technology; Multichip modules; Numerical analysis; Prototypes; Redundancy; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Instrumentation and Measurement Technology Conference, 2001. IMTC 2001. Proceedings of the 18th IEEE
  • Conference_Location
    Budapest
  • ISSN
    1091-5281
  • Print_ISBN
    0-7803-6646-8
  • Type

    conf

  • DOI
    10.1109/IMTC.2001.928813
  • Filename
    928813