A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter

Author

Jiang, Jiandong ; Lee, Edward K F

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

2001

fDate

2001

Firstpage

165

Lastpage

168

Abstract

A direct digital frequency synthesizer (DDFS) based on nonlinear digital-to-analog converter (DAC) is presented. A new technique is proposed to segment the nonlinear DAC such that high speed DDFS with low power consumption and small die area can be achieved. The DDFS has 12 bits of phase resolution and 11 bits of magnitude resolution. It was fabricated in a 0.25 μm CMOS process with an active area of 1.4 mm ². For a clock frequency of 300 MHz, the spurious free dynamic range (SFDR) is better than 50 dB with output frequencies up to 3/8 of the clock frequency

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital-analogue conversion; direct digital synthesis; high-speed integrated circuits; low-power electronics; 0.25 micron; 300 MHz; CMOS process; ROM-less DDS; digital-to-analog converter; direct digital frequency synthesizer; high speed DDS; low power consumption; segmented nonlinear DAC; small die area; CMOS process; Clocks; Digital circuits; Digital-analog conversion; Energy consumption; Frequency synthesizers; Laboratories; Power dissipation; Read only memory; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929748

Filename

929748