DocumentCode
1747861
Title
Estimation of speed, area, and power of parameterizable, soft IP
Author
Sanghavi, Jagesh ; Wang, Albert
Author_Institution
Tensilica Inc., USA
fYear
2001
fDate
2001
Firstpage
31
Lastpage
34
Abstract
We present a new approach to estimate speed, area, and power of a parameterizable, soft IP. By running the ASIC implementation flow only on selected configurations, we predict the performance for any arbitrary configuration. We exploit performance function decomposability to address the combinatorial explosion challenge. The estimator has been used successfully to configure Xtensa processor cores for numerous embedded SOC designs.
Keywords
VLSI; application specific integrated circuits; industrial property; integrated circuit design; logic CAD; software libraries; ASIC implementation flow; Xtensa processor cores; combinatorial explosion challenge; embedded SOC designs; parameterizable IP; performance function decomposability; soft IP; Application specific integrated circuits; Costs; Digital signal processing; Explosions; Extraterrestrial measurements; Feedback; Parameter estimation; Permission; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2001. Proceedings
ISSN
0738-100X
Print_ISBN
1-58113-297-2
Type
conf
DOI
10.1109/DAC.2001.156103
Filename
935472
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