DocumentCode
1757332
Title
Counterexample Ranking Using Mined Invariants
Author
Mitra, Subhasish ; Banerjee, Adrish ; Dasgupta, Parthasarathi ; Kumar, Harish
Author_Institution
IBM India Pvt. Ltd., Bangalore, India
Volume
32
Issue
12
fYear
2013
fDate
Dec. 2013
Firstpage
1978
Lastpage
1991
Abstract
Bug-fixing in deeply embedded portions of the logic is typically accompanied by the postfacto addition of new assertions, which cover the bug scenario. Formally verifying the assertions defined over such deeply embedded portions of the logic is challenging because formal methods do not scale to the size of the entire logic. Verifying the assertion on the embedded logic in isolation typically throws up a large number of counterexamples, many of which are spurious because the scenarios they depict are not possible in the entire logic. In this paper, we introduce the notion of ranking the counterexamples so that only the most likely counterexamples are presented to the designer. Our ranking is based on assume properties mined from simulation traces of the entire logic. We define a metric to compute a belief for each assume property that is mined, and rank counterexamples based on their relationships with the mined assume properties. Experimental results demonstrate a remarkable correlation between the real counterexamples (if they exist) and the proposed ranking metric, thereby establishing the proposed method as a very promising verification approach.
Keywords
decision trees; embedded systems; formal verification; logic design; bug fixing; counterexample ranking; embedded logic; formal methods; formal verification; logic design; mined invariants; ranking metric; Bayes methods; Decision trees; Formal verification; Simulation; Bayes methods; decision trees; formal verification; simulation;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2013.2276627
Filename
6663245
Link To Document